Seminar: Advances in Computer Systems 2019

Weekly outline

• Select week General

  General

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  • Select activity Announcements

    

    Announcements Forum
  • Select activity General info Each student will give a presentatio...

    General info

    Each student will give a presentation based on papers recommended by Onur Mutlu, renowned researcher in the area of computer systems. He conducts a course in Computer Systems for graduate students at ETH Zurich on yearly basis.

  • Select activity Grading A student can obtain at most 72 points th...

    Grading

    A student can obtain at most 72 points through following means:

    • presentation (up to 48 points, 16 points for one-hour slot)
    • attendance + activity (up to 2 points for each week)

    Points	Grade
    66 – 72	5.0
    59 – 65	4.5
    52 – 58	4.0
    45 – 51	3.5
    36 – 44	3.0

    By attending single seminar a student gets one point. To get the other point one should ask questions during a presentation. After the presentation they must give a feedback to the speaker (regarding quality of slides, structure of the presentation, etc.).

    For each student there should be enough time during the semester to give one 2-hour and one 1-hour presentation. If a student misses assigned time slots, for whatever reason, (s)he might not get a chance to score points.

  • Select activity Recommended papers DRAM ISCA 2014 Flipping Bit...

    Recommended papers

    DRAM

    • ISCA 2014 Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors Y. Kim, R. Daly, J. Kim, C. Fallin, J.H. Lee, D. Lee, C. Wilkerson, K. Lai, O. Mutlu
    • HPCA 2013 Tiered-Latency DRAM: A Low Latency and Low Cost DRAM Architecture Donghyuk Lee, Yoongu Kim, Vivek Seshadri, Jamie Liu, Lavanya Subramanian, and Onur Mutlu
    • ISCA 2012 A Case for Exploiting Subarray-Level Parallelism (SALP) in DRAM Yoongu Kim, Vivek Seshadri, Donghyuk Lee, Jamie Liu, and Onur Mutlu
    • ISCA 2012 RAIDR: Retention-Aware Intelligent DRAM Refresh Jamie Liu, Ben Jaiyen, Richard Veras, and Onur Mutlu

    Caches

    • ISCA 2006 A Case for MLP-Aware Cache Replacement Moinuddin K. Qureshi, Daniel N. Lynch, Onur Mutlu, and Yale N. Patt
    • ISCA 2007 Adaptive Insertion Policies for High Performance Caching M. K. Qureshi, A. Jaleel, Y. N. Patt, S. C. Steely Jr., J. Emer
    • PACT 2012 The Evicted-Address Filter: A Unified Mechanism to Address Both Cache Pollution and Thrashing V. Seshadri, O. Mutlu, M. A Kozuch, T. C Mowry
    • PACT 2012 Base-Delta-Immediate Compression: Practical Data Compression for On-Chip Caches G. Pekhimenko, V. Seshadri, O. Mutlu, P. B Gibbons, M. A Kozuch, T. C Mowry

    Branch prediction

    • HPCA 2001 Dynamic Branch Prediction with Perceptrons Jimenez and C. Lin
    • JILP 2006 A Case for (Partially) TAgged GEometric History Length Branch Prediction A. Seznec and P. Michaud

    Parallel processing

    • MICRO 2007 Dynamic Warp Formation and Scheduling for Efficient GPU Control Flow W.W.L. Fung, I. Sham, G. Yuan, and T.M. Aamodt
    • INPAR 2012 DL: A Data Layout Transformation System for Heterogeneous Computing I.J. Sung, G.D. Liu, W.M. Hwu

    In-memory processing

    • ISCA 2015 A Scalable Processing-in-Memory Accelerator for Parallel Graph Processing Junwhan Ahn, Sungpack Hong, Sungjoo Yoo, Onur Mutlu, and Kiyoung Choi
    • ASPLOS 2018 Google Workloads for Consumer Devices: Mitigating Data Movement Bottlenecks A. Boroumand, S. Ghose, Y. Kim, R. Ausavarungnirun, E. Shiu, R. Thakur, D. Kim, A. Kuusela, A. Knies, P. Ranganathan, and O. Mutlu
    • MICRO 2017 Ambit: In-Memory Accelerator for Bulk Bitwise Operations Using Commodity DRAM Technology V. Seshadri, D. Lee, T. Mullins, H. Hassan, A. Boroumand, J. Kim, M.A. Kozuch, O. Mutlu, P.B. Gibbons, T.C. Mowry
    • ISCA 2016 Accelerating Dependent Cache Misses with an Enhanced Memory Controller Milad Hashemi, Khubaib, Eiman Ebrahimi, Onur Mutlu, and Yale N. Patt

    Multi-core cache management

    • PACT 2004 Fair Cache Sharing and Partitioning in a Chip Multiprocessor Architecture S. Kim, D. Chandra, Y. Solihin
    • MICRO 2006 Managing Distributed, Shared L2 Caches through OS-Level Page Allocation S. Cho and L. Jin

    Interconnect

    • SIGCOMM 2012 On-Chip Networks from a Networking Perspective: Congestion and Scalability in Many-core Interconnects G. Nychis, C. Fallin, T. Moscibroda, O. Mutlu, and S. Seshan
    • HPCA 2011 CHIPPER: A Low-Complexity Bufferless Deflection Router Chris Fallin, Chris Craik, and Onur Mutlu
  • Select activity Links

    Links

  • Select activity Onur Multu: Computer Architecture (Fall 2019)

    

    Onur Multu: Computer Architecture (Fall 2019) URL

    Lectures on YouTube, slides, papers and more.

  • Select activity Onur Multu: Computer Architecture (Fall 2018)

    

    Onur Multu: Computer Architecture (Fall 2018) URL

    Lectures on YouTube, slides, papers and more.

  • Select activity Onur Multu: Computer Architecture (Fall 2017)

    

    Onur Multu: Computer Architecture (Fall 2017) URL

    Lectures on YouTube, slides, papers and more.

  • Select activity WikiChip

    

    WikiChip URL
  • Select activity Books

    Books

• Select week October 8th, 2019

  October 8th, 2019
  • Select activity Indistinguishable From Magic: Manufacturing Modern Computer Chips

    

    Indistinguishable From Magic: Manufacturing Modern Computer Chips URL
• Select week 15th October, 2019

  15th October, 2019

  Jan Mazur (2h)

  Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors

  • Select activity Absentees: Paweł Jasiak (sickleave)

    Absentees: Paweł Jasiak (sickleave)

  • Select activity Jan Mazur: Flipping Bits in Memory Without Accessing Them

    

    Jan Mazur: Flipping Bits in Memory Without Accessing Them File
• Select week October 22nd, 2019

  October 22nd, 2019

  Zbigniew Drozd (2h)

   CHIPPER: A Low-Complexity Bufferless Deflection Router 

  • Select activity Zbigniew Drozd: Ein kurzer Vortrag über pufferlose Ablenkrouter

    

    Zbigniew Drozd: Ein kurzer Vortrag über pufferlose Ablenkrouter File
• Select week October 29th, 2019

  October 29th, 2019

  Julian Pszczołowski (2h)

  Google Workloads for Consumer Devices: Mitigating Data Movement Bottlenecks 

  • Select activity Julian Pszczołowski: Google Workloads for Consumer Devices Mitigating Data Movement Bottlenecks

    

    Julian Pszczołowski: Google Workloads for Consumer Devices Mitigating Data Movement Bottlenecks File
• Select week November 5th, 2019

  November 5th, 2019

  Enrique Mellado Gómez (2h)

  Dynamic Warp Formation and Scheduling for Efficient GPU Control Flow
• Select week November 12th, 2019

  November 12th, 2019

  Salvador Delgado Arroyo (2h)

  Accelerating Dependent Cache Misses with an Enhanced Memory Controller

  • Select activity Absentees: Wojciech Moczulski

    Absentees: Wojciech Moczulski

• Select week November 19th, 2019

  November 19th, 2019

  Paweł Dybiec (2h)

  • Select activity Absentees: Wojciech Moczulski (copy)

    Absentees: Wojciech Moczulski

  • Select activity Introduction to modern GPU architecture

    

    Introduction to modern GPU architecture File
• Select week November 26th, 2019

  November 26th, 2019

  Paweł Jasiak (2h)

  Base-Delta-Immediate Compression: Practical Data Compression for On-Chip Caches

  • Select activity Absentees: Enrique Mellado Gómez, Salvador Delgado...

    Absentees: Enrique Mellado Gómez, Salvador Delgado Arroyo

  • Select activity Practical Data Compression for On-Chip Caches

    

    Practical Data Compression for On-Chip Caches File
  • Select activity Spec2006 benchmark description

    

    Spec2006 benchmark description File
• Select week December 3rd, 2019

  December 3rd, 2019

  Patrycja Balik (2h)

  Adaptive Insertion Policies for High Performance Caching

  • Select activity Absentees: Enrique Mellado Gómez, Salvador Delgado...

    Absentees: Enrique Mellado Gómez, Salvador Delgado Arroyo, Jan Mazur, Julian Pszczołowski, Wojciech Moczulski

  • Select activity Adaptive cache insertion policies

    

    Adaptive cache insertion policies File
• Select week December 10th, 2019

  December 10th, 2019

  No speaker this week. We were watching lecture about prefetching:
• Select week December 17th, 2019

  December 17th, 2019

  No speaker this week. We were watching lecture about multiprocessors, consistency and coherence:
• Select week January 14th, 2020

  January 14th, 2020

  Meeting cancelled due to missing speaker and coordinator being sick.
• Select week January 21st, 2020

  January 21st, 2020

  Paweł Jasiak (1h)

  • Select activity Managing Distributed, Shared L2 Caches through OS-Level Page Allocation

    

    Managing Distributed, Shared L2 Caches through OS-Level Page Allocation File
• Select week January 28th, 2020

  January 28th, 2020

  Zbigniew Drozd (1h)

  • Select activity Low Latency and Low Cost DRAM Architecture

    

    Low Latency and Low Cost DRAM Architecture File
• Select week February 4th, 2020

  February 4th, 2020

  Julian Pszczołowski (1h)

  • Select activity Improving C/C++ memory safety using hardware-assisted sanitizers and memory tagging

    

    Improving C/C++ memory safety using hardware-assisted sanitizers and memory tagging File
• Select week Extra meeting

  Extra meeting

  Jan Mazur (1h)

  Patrycja Balik (1h)

  Paweł Dybiec (1h)